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| HT46R46E/HT46C46E Cost-Effective A/D Type 8-Bit MCU Technical Document * Tools Information * FAQs * Application Note - HA0049E Read and Write Control of the HT1380 - HA0051E Li Battery Charger Demo Board - Using the HT46R47 - HA0052E Microcontroller Application - Battery Charger - HA0083E Li Battery Charger Demo Board - Using the HT46R46 - HA0085E 8-bit Pseudo-Random Number Generator Features * Operating voltage: * HALT function and wake-up feature reduce power fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V * 13 bidirectional I/O lines (max.) * 1 interrupt input shared with an I/O line * 8-bit programmable timer/event counter with overflow consumption * Up to 0.5ms instruction cycle with 8MHz system clock at VDD=5V * 4-level subroutine nesting * 4 channels 8-bit resolution A/D converter * 1 channel 8-bit PWM output shared with an I/O line * Bit manipulation instruction * 14-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * Low voltage reset function * 18-pin DIP/SOP package interrupt and 7-stage prescaler * On-chip crystal and RC oscillator * Watchdog Timer * 102414 program memory * 648 data memory RAM * 1288 data EEPROM * Supports PFD for sound generation General Description The HT46R46E/HT46C46E are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The mask version HT46C46E is fully pin and functionally compatible with the OTP version HT46R46E device. There are two dice in the HT46R46E/HT46C46E package: one is the HT46R46/HT46C46 MCU, the other is a 1288 bits EEPROM used for data memory purpose. The two dice are wire-bonded to form HT46R46E/ HT46C46E. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, HALT and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. Rev. 1.30 1 July 19, 2005 HT46R46E/HT46C46E Block Diagram HT46R46E/HT46C46E P A 5 /IN T In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C TM RC TM R P A 3 /P F D In s tr u c tio n R e g is te r W DT P r e s c a le r PW M PDC PD In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r PA3,PA5 MUX 4 -C h a n n e l A /D C o n v e rte r STATUS PBC PB P o rt B P B 0 /A N 0 ~ P B 2 /A N 2 S C L /P B 3 /A N 3 PA PA PA PA PA 0~P 3 /P 4 /T 5 /IN 6,P A2 FD MR T A7 P o rt D M U X PA4 P r e s c a le r P A 4 /T M R fS YS fS M U X YS /4 MP M U X D a ta M e m o ry WDT RC S D A /P D 0 /P W M OSC PAC OSC2 OS RE VD VS S S D C1 ACC LVR PA P o rt A Data EEPROM SCL SDA I/O C o n tro l L o g ic X D M e m o ry C o n tro l L o g ic C E HV Pum p EEPROM A rra y Page Buf YDEC A d d re s s C o u n te r VCC VSS S ense A M P R /W C o n tro l Rev. 1.30 2 July 19, 2005 HT46R46E/HT46C46E Pin Assignment P A 3 /P F D 1 2 3 4 5 6 7 8 9 PA2 PA1 PA0 S C L /P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS 18 17 16 15 14 13 12 11 10 P A 4 /T M R P A 5 /IN T PA6 PA7 OSC2 OSC1 VDD RES S D A /P D 0 /P W M H T 4 6 R 4 6 E /H T 4 6 C 4 6 E 1 8 D IP -A /S O P -A Pad Description Pad Name PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6, PA7 PB0/AN0 PB1/AN1 PB2/AN2 SCL/PB3/AN3 I/O Options Pull-high Wake-up PA3 or PFD Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by options. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). The PFD, TMR and INT are pin-shared with PA3, PA4 and PA5, respectively. Bidirectional 4-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically. PB3/AN3 is wire-bonded with SCL pad of the Data EEPROM Bidirectional I/O line. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high options: bit option). The PWM output function is pin-shared with PD0 (dependent on PWM options). PD0/PWM is wire-bonded with SDA pad of the Data EEPROM. Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground. OSC1, OSC2 are connected to an RC network or a Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. I/O I/O Pull-high SDA/PD0/PWM I/O Pull-high PD0 or PWM RES VDD VSS OSC1 OSC2 I 3/4 3/4 I O 3/4 3/4 3/4 Crystal or RC Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.30 3 July 19, 2005 HT46R46E/HT46C46E D.C. Characteristics HT46R46/HT46C46 Test Conditions Symbol Parameter VDD VDD Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset I/O Port Sink Current 5V IOH 3V I/O Port Source Current 5V RPH VAD EAD IADC 3V Pull-high Resistance 5V A/D Input Voltage A/D Conversion Error Additional Power Consumption if A/D Converter is Used 3/4 3/4 3V 5V 3/4 3/4 3V 5V 3V 5V 5V 3V 5V 3V 5V 3/4 3/4 3/4 3/4 3/4 3V Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz ADC disable No load, fSYS=4MHz ADC disable No load, fSYS=8MHz ADC disable No load, system HALT No load, system HALT 3/4 3/4 3/4 3/4 3/4 VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD 3/4 3/4 3/4 3/4 3/4 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 20 10 0 3/4 3/4 3/4 3/4 3/4 0.6 2 0.8 2.5 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3 8 20 -4 -10 60 30 3/4 0.5 0.5 1.5 5.5 5.5 1.5 4 1.5 4 8 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4 100 50 VDD 1 1 3 V V mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA kW kW V LSB mA mA Min. Typ. Max. Unit Ta=25C IDD1 IDD2 IDD3 ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 VLVR IOL Rev. 1.30 4 July 19, 2005 HT46R46E/HT46C46E EEPROM D.C. Characteristics Test Conditions Symbol VCC ICC1 ICC2 VIL VIH VOL ILI ILO ISTB1 ISTB2 CIN COUT Note: Parameter VCC Operating Voltage Operating Current Operating Current Input Low Voltage Input High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Standby Current Standby Current Input Capacitance (See Note) Output Capacitance (See Note) 3/4 5V 5V 3/4 3/4 2.4V 5V 5V 5V 2.4V 3/4 3/4 Conditions 3/4 Read at 100kHz Write at 100kHz 3/4 3/4 IOL=2.1mA VIN=0 or VCC VOUT=0 or VCC VIN=0 or VCC VIN=0 or VCC f=1MHz 25C f=1MHz 25C 2.2 3/4 3/4 -1 0.7VCC 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 5.5 2 5 0.3VCC VCC+0.5 0.4 1 1 4 3 6 8 V mA mA V V V mA mA mA mA pF pF Min. Typ. Max. Unit Ta=25C These parameters are periodically sampled but not 100% tested VCC pad is wire-bonded to VDD pad of the HT46R46/HT46C46 die. A.C. Characteristics HT46R46/HT46C46 Test Conditions Symbol Parameter VDD fSYS System Clock Timer I/P Frequency (TMR) Watchdog Oscillator Period 5V tWDT1 tWDT2 tRES tSST tINT tAD tADC tADCS Watchdog Time-out Period (RC) Watchdog Time-out Period (System Clock) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 400 400 0 0 45 32 215 217 1 3/4 1 0.5 3/4 3/4 3/4 3/4 3/4 3/4 90 65 3/4 3/4 3/4 1024 3/4 3/4 64 32 4000 8000 4000 8000 180 130 216 218 3/4 3/4 3/4 3/4 3/4 3/4 Min. Typ. Max. Ta=25C Unit kHz kHz kHz kHz ms ms tWDTOSC tSYS ms *tSYS ms ms tAD tAD fTIMER tWDTOSC Note: *tSYS=1/fSYS Rev. 1.30 5 July 19, 2005 HT46R46E/HT46C46E EEPROM A.C. Characteristics Standard Mode* Symbol fSK tHIGH tLOW tr tf tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tAA tBUF Parameter Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time START Condition Setup Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Bus Free Time Input Filter Time Constant (SDA and SCL Pins) Write Cycle Time Note Note After this period the first clock pulse is generated Only relevant for repeated START condition 3/4 3/4 3/4 3/4 Time in which the bus must be free before a new transmission can start Noise suppression time 3/4 Remark Min. 3/4 3/4 3/4 3/4 4000 4700 3/4 3/4 4000 4000 0 200 4000 3/4 4700 Max. 100 3/4 3/4 1000 300 3/4 3/4 3/4 3/4 3/4 3500 3/4 VCC=5V10% Min. 3/4 600 1200 3/4 3/4 600 600 0 100 600 3/4 1200 Max. 400 3/4 3/4 300 300 3/4 3/4 3/4 3/4 3/4 900 3/4 kHz ns ns ns ns ns ns ns ns ns ns ns Ta=25C Unit tSP tWR Note: 3/4 3/4 100 5 3/4 3/4 50 5 ns ms These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.2V to 5.5V For relative timing, refer to timing diagrams Rev. 1.30 6 July 19, 2005 HT46R46E/HT46C46E Functional Description Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. S y s te m C lo c k O S C 2 ( R C o n ly ) PC PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Program Counter Mode *9 Initial Reset External Interrupt Timer/Event Counter Overflow A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 *6 0 0 0 0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0 Program Counter+2 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 Program Counter Note: *9~*0: Program counter bits #9~#0: Instruction code bits 7 S9~S0: Stack register bits @7~@0: PCL bits July 19, 2005 Rev. 1.30 HT46R46E/HT46C46E Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 102414 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: * Location 000H * Location 00CH This area is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. * Table location This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H. * Location 004H This area is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H. * Location 008H This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H. 000H 004H 008H 00C H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 2 bits are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the n00H nFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 300H 3FFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 3 Program Memory Table Location Instruction *9 TABRDC [m] TABRDL [m] P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *9~*0: Table location bits @7~@0: Table pointer bits P9~P8: Current program counter bits Rev. 1.30 8 July 19, 2005 HT46R46E/HT46C46E stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 4 return addresses are stored). Data Memory - RAM The data memory is designed with 848 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (648). Most are read/write, but some are read only. The special function registers include the indirect addressing register (00H), timer/event counter (TMR;0DH), timer/event counter control register (TMRC;0EH), program counter lower-order byte register (PCL;06H), memory pointer register (MP;01H), accumulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC;0BH), PWM data register (PWM;1AH), the A/D result register (ADR;21H), the A/D control register (ADCR;22H), the A/D clock setting register (ACSR;23H), I/O registers (PA;12H, PB;14H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PDC;19H). The remaining space before the 40H is reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer register (MP;01H). Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed to by MP (01H). Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer register MP (01H) is a 7-bit register. The bit 7 of MP is undefined and reading will return the result 1. Any writing operation to MP will only transfer the lower 7-bit data to MP. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 3FH 40H ADR ADCR ACSR PD PDC PW M PA PAC PB PBC S p e c ia l P u r p o s e DATA M EM ORY TM R TM RC STATUS IN T C ACC PCL TBLP TBLH In d ir e c t A d d r e s s in g R e g is te r MP G e n e ra l P u rp o s e DATA M EM ORY (6 4 B y te s ) :U nused R e a d a s "0 0 " 7FH RAM Mapping Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: * Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....) Rev. 1.30 9 July 19, 2005 HT46R46E/HT46C46E The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt, internal timer/event counter interrupt and A/D converter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF;bit 5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. Bit No. 0 Label C Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register 1 2 3 4 5 6, 7 AC Z OV PDF TO 3/4 Rev. 1.30 10 July 19, 2005 HT46R46E/HT46C46E Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ETI EADI EIF TF ADF 3/4 Function Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled) Controls the A/D converter interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter request flag (1=active; 0=inactive) A/D converter request flag (1=active; 0=inactive) For test mode used only. Must be written as 0; otherwise may result in unpredictable operation. INTC (0BH) Register The A/D converter interrupt is initialized by setting the A/D converter request flag (ADF; bit 6 of INTC), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt Timer/Event Counter Overflow A/D Converter Interrupt Priority 1 2 3 Vector 04H 08H 0CH It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There are two oscillator circuits in the microcontroller. V OSC1 DD 470pF OSC1 OSC2 C r y s ta l O s c illa to r fS YS /4 OSC2 R C O s c illa to r System Oscillator Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined by the options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 30kW to 750kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request flag (ADF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI) and enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ETI, EADI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF, ADF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. Rev. 1.30 11 July 19, 2005 HT46R46E/HT46C46E If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz). The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65ms@5V. The WDT oscillator can be disabled by options to conserve power. Watchdog Timer - WDT The clock source of WDT is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by options. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by an option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal oscillator (RC oscillator with a period of 65ms@5V normally) is selected, it is divided by 32768~65536 to get the time-out period of approximately 2.1s~4.3s. This time-out period may vary with temperatures, VDD and process variations. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset, and only the program counter and SP are reset to zero. To clear the contents of WDT, three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can S y s te m C lo c k /4 O p tio n S e le c t W DT OSC fS 8 - b it C o u n te r 7 - b it C o u n te r T T W D T T im e - o u t 15 16 fS /2 ~ fS /2 CLR W DT be active depending on the options - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following... * The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected). * The contents of the on chip RAM and registers remain unchanged. * WDT will be cleared and recounted again (if the WDT clock is from the WDT oscillator). * All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others keep their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Watchdog Timer Rev. 1.30 12 July 19, 2005 HT46R46E/HT46C46E Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur: * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation 100kW RES 10kW 0 .1 m F * The functional unit chip reset status are shown below. Program Counter Interrupt WDT 000H Disable Clear. After master reset, WDT begins counting Timer/Event Counter Off Input/Output Ports Stack Pointer Input mode Points to the top of the stack V DD 0 .0 1 m F * The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. VDD RES S S T T im e - o u t C h ip R eset tS ST Reset Timing Chart Note: u means unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). HALT W DT RES W a rm R eset OSC1 SST 1 0 - b it R ip p le C o u n te r S y s te m R eset C o ld R eset Reset Configuration Rev. 1.30 13 July 19, 2005 HT46R46E/HT46C46E The registers states are summarized in the following table. Register TMR TMRC Program Counter MP ACC TBLP TBLH STATUS INTC PA PAC PB PBC PD PDC PWM ADR ADCR ACSR Note: Reset (Power On) xxxx xxxx 00-0 1000 000H -xxx xxxx xxxx xxxx xxxx xxxx --xx xxxx --00 xxxx -000 0000 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- ---1 ---- ---1 xxxx xxxx xxxx xxxx 0100 0000 1--- --00 * stands for warm reset u stands for unchanged x stands for unknown The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the fINT. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bits is 0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle 14 July 19, 2005 WDT Time-out RES Reset (Normal Operation) (Normal Operation) xxxx xxxx 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --1u uuuu -000 0000 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- ---1 ---- ---1 xxxx xxxx xxxx xxxx 0100 0000 1--- --00 xxxx xxxx 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu -000 0000 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- ---1 ---- ---1 xxxx xxxx xxxx xxxx 0100 0000 1--- --00 RES Reset (HALT) xxxx xxxx 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --01 uuuu -000 0000 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- ---1 ---- ---1 xxxx xxxx xxxx xxxx 0100 0000 1--- --00 WDT Times-out (HALT)* uuuu uuuu uu-u uuuu 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu ---- ---u ---- ---u uuuu uuuu uuuu uuuu uuuu uuuu u--- --uu Timer/Event Counter A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or the system clock. Using external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. The timer/event counter can generate PFD signal by using external or internal clock and PFD frequency is determine by the equation fINT/[2(256-N)]. There are 2 registers related to the timer/event counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in the timer/event counter preload register and reading TMR retrieves the contents of the timer/event counter. The TMRC is a timer/event counter control register, which defines some options. Rev. 1.30 HT46R46E/HT46C46E measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt service. Bit No. Label In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. Function To define the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR active edge of the timer/event counter: In Event Counter Mode (TM1,TM0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (TM1,TM0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge To enable or disable timer counting (0=disabled; 1=enabled) Unused bits, read as 0 To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (0EH) Register PW M 0 1 2 PSC0 PSC1 PSC2 3 TE 4 5 TON 3/4 TM0 TM1 6 7 (6 + 2 ) C o m p a re fS YS T o P D 0 C ir c u it 8 - s ta g e P r e s c a le r 8 -1 M U X PSC2~PSC0 TM R TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r 1 /2 O v e r flo w to In te rru p t PFD f IN T D a ta B u s TM 1 TM 0 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d Timer/Event Counter Rev. 1.30 15 July 19, 2005 HT46R46E/HT46C46E Input/Output Ports There are 13 bidirectional input/output lines in the microcontroller, labeled as PA, PB and PD, which are mapped to the data memory of [12H], [14H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H and 19H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H or 18H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The highest 4-bit of port B and 7 bits of port D are not physically implemented; on reading them a 0 is returned whereas writing then results in a no-operation. See Application note. Each I/O line has a pull-high option. Once the pull-high option is selected, the I/O line has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O line operating in input mode will cause a floating state. The PA3 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by the timer/event counter overflow signal. The input mode always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data register only. Writing 1 to PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain at 0. The I/O functions of PA3 are shown below. I/O Mode PA3 Note: I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PFD) O/P (PFD) Logical PFD Input (Timer on) The PFD frequency is the timer/event counter overflow frequency divided by 2. V DD C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D CK Q QB S PU D a ta B it Q D CK QB S M U X PFDEN (P A 3 ) U X O P0~O P7 W r ite D a ta R e g is te r PA PA PA PA PA PB SC SD 0~P 3 /P 4 /T 5 /IN 6,P 0 /A L /P A /P A2 FD MR T A7 N 0 ~ P B 2 /A N 2 B 3 /A N 3 D 0 /P W M (P D 0 o r P W M ) PA3 PFD M R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T fo r P A 5 O n ly TM R fo r P A 4 O n ly Input/Output Ports Rev. 1.30 16 July 19, 2005 HT46R46E/HT46C46E The PA5 and PA4 are pin-shared with INT and TMR pins respectively. The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0. If the PWM function is enabled, the PWM signal will appear on PD0 (if PD0 is operating in output mode). Writing 1 to PD0 data register will enable the PWM output function and writing 0 will force the PD0 to remain at 0. The I/O functions of PD0 are as shown. I/O Mode PD0 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM the PWM output function and writing 0 will force the PD0 to stay at 0. A PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. In a PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) i The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency fSYS/64 PWM Cycle Frequency fSYS/256 PWM Cycle Duty [PWM]/256 fS YS /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 YS 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 M o d u la tio n c y c le 1 PW M 2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS YS 2 5 /6 4 M o d u la tio n c y c le 3 2 6 /6 4 M o d u la tio n c y c le 0 PWM Rev. 1.30 17 July 19, 2005 HT46R46E/HT46C46E A/D Converter The 4 channels and 8-bit resolution A/D converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 3 special registers which are; ADR (21H), ADCR (22H) and ACSR (23H). The ADR is an A/D result register that is read-only. After the A/D conversion is completed, the ADR should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion, define PB configuration, select the converted analog channel, and give START bit a raising edge and a falling edge (0(R)1(R)0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of four channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled, and the A/D converter circuit is power on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of A/D converter. Give START bit a raising edge and falling edge that means the A/D conversion has started. In order to ensure the A/D conversion is completed, the START should stay at 0 until the EOCB is cleared to 0 (end of A/D conversion). Bit 7 of the ACSR register is used for test purposes only and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are used to select the A/D clock source. When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Important Note for A/D initialization: Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required. Bit7 D7 Note: Bit6 D6 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0 D0~D7 is A/D conversion result data bit LSB~MSB. ADR (21H) Register Bit No. Label ACS2, ACS1, ACS0: Select A/D channel 0, 0, 0: AN0 0, 0, 1: AN1 0, 1, 0: AN2 0, 1, 1: AN3 1, X, X: undefined, cannot be used Function 0 1 2 ACS0 ACS1 ACS2 3 4 5 PCR0 PCR1 PCR2 PCR2, PCR1, PCR0: PB3~PB0 configurations 0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce power consumption.) 0, 0, 1: PB3 PB2 PB1 AN0 0, 1, 0: PB3 PB2 AN1 AN0 0, 1, 1: PB3 AN2 AN1 AN0 1, x, x: AN3 AN2 AN1 AN0 Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialization. 6 EOCB 7 Start the A/D conversion START 0(R)1(R)0= Start 0(R)1= Reset A/D converter and set EOCB to 1 ADCR (22H) Register Rev. 1.30 18 July 19, 2005 HT46R46E/HT46C46E Bit No. Label Select the A/D converter clock source. 0, 0: fSYS/2 0, 1: fSYS/8 1, 0: fSYS/32 1, 1: Undefined Unused bit, read as 0. For internal test only. ACSR (23H) Register The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr mov mov mov mov EADI a,00000001B ACSR,a a,00100000B ADCR,a : : ; disable ADC interrupt ; setup the ACSR register to select fSYS/8 as the A/D clock ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles Function 0 1 ADCS0 ADCS1 3/4 TEST 2~6 7 : Start_conversion: clr START set START clr START Polling_EOC: sz EOCB jmp polling_EOC mov a,ADR mov adr_buffer,a : : jmp start_conversion ; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result value from the ADR register ; save result to user defined memory ; start next A/D conversion Example: using interrupt method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : Rev. 1.30 ; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt 19 July 19, 2005 HT46R46E/HT46C46E : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADR mov adr_buffer,a clr START set START clr START : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack reti ; save ACC to user defined memory ; save STATUS to user defined memory ; read conversion result value from the ADR register ; save result to user defined register ; reset A/D ; start A/D ; restore STATUS from user defined memory ; restore ACC from user defined memory M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d EOCB PC R2~ PCR0 A /D tA 000B DCS s a m p lin g tim e 100B A /D tA DCS s a m p lin g tim e A /D tA DCS s a m p lin g tim e 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n 100B 101B AC S2~ ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D tA D tA CS 010B S ta rt o f A /D c o n v e r s io n 000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n d o n 't c a r e E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e tA D C c o n v e r s io n tim e YS A /D tA D C c o n v e r s io n tim e A /D DC c lo c k m u s t b e fS = 3 2 tA D = 6 4 tA D YS /2 , fS /8 o r fS YS /3 2 A/D Conversion Timing Rev. 1.30 20 July 19, 2005 HT46R46E/HT46C46E Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~3.3V, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: * The low voltage (0.9V~VLVR) has to remain in their Options The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper system functioning. No. 1 2 3 4 5 6 7 8 9 Options WDT clock source: WDTOSC or fTID WDT function: enable or disable CLRWDT instruction(s): one or two clear WDT instruction(s) System oscillator: RC or crystal Pull-high resistors (PA, PB, PD): none or pull-high PWM enable or disable PA0~PA7 wake-up: enable or disable PFD enable or disable Low voltage reset selection: enable or disable LVR function. original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. * The LVR uses the OR function with the external RES signal to perform chip reset. The relationship between VDD and VLVR is shown below. V DD V OPR 5 .5 V 5 .5 V V 3 .0 V 2 .2 V LVR 0 .9 V Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. V 5 .5 V DD V LVR LVR D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the reset mode. Rev. 1.30 21 July 19, 2005 HT46R46E/HT46C46E Data EEPROM Functional Description * Serial clock (SCL) Device Addressing The 1K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the Device Address). This is common to all the EEPROM device. The next three bits are the fixed to be 0. The 8th bit of device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state. 1 0 1 0 0 0 0 R /W The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device. * Serial data (SDA) The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. Memory Organization * 1K Serial EEPROM Internally organized with 128 8-bit words, the 1K requires an 8-bit data word address for random word addressing. Device Operations * Clock and data transition Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition. * Start condition D e v ic e A d d r e s s Write Operations * Byte write A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram). * Stop condition A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram). * Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. D a ta a llo w e d to c h a n g e SDA A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the non-volatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write is completed (refer to Byte write timing). * Acknowledge polling To maximise bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received. SCL S ta rt c o n d itio n A d d re s s o r a c k n o w le d g e v a lid NoACK s ta te S to p c o n d itio n D e v ic e a d d r e s s SDA S S ta rt R /W ACK W o rd a d d re s s DATA P ACK ACK S to p Byte Write Timing Rev. 1.30 22 July 19, 2005 HT46R46E/HT46C46E S e n d W r ite C o m m a n d S e n d S to p C o n d itio n to In itia te W r ite C y c le S e n d S ta rt S e n d C o tr o ll B y te w ith R /W = 0 page. The address roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller should respond a No ACK (High) signal and following stop condition (refer to Current read timing). * Random read (A C K = 0 )? Yes N e x t O p e r a tio n No Acknowledge Polling Flow * Read operations A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller should respond with a no ACK signal (high) followed by a stop condition. (refer to Random read timing). * Sequential read The data EEPROM supports three read operations, namely, current address read, random address read and sequential read. During read operation execution, the read/write select bit should be set to 1. * Current address read The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll over during read from the last byte of the last memory page to the first byte of the first D e v ic e a d d r e s s SDA S S ta rt ACK Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller responds with a no ACK signal (high) followed by a stop condition. DATA S to p P NoACK Current Read Timing D e v ic e a d d r e s s SDA S W o rd a d d re s s S D e v ic e a d d r e s s DATA S to p P NoACK S ta rt ACK ACK S ta rt ACK Random Read Timing D e v ic e a d d r e s s SDA S DATA n DATA n+1 DATA n+x S to p P NoACK S ta rt ACK ACK Sequential Read Timing Rev. 1.30 23 July 19, 2005 HT46R46E/HT46C46E Data EEPROM Timing Diagrams tf SCL tS U tr tL OW D tH IG H :S TA tH tS P :S TA tH D :D AT tS U :D AT tS U :S TO SDA SDA OUT tA A tB V a lid V a lid UF SCL SDA 8 th b it W o rd n S to p C o n d itio n ACK tW R S ta rt C o n d itio n Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command. Rev. 1.30 24 July 19, 2005 HT46R46E/HT46C46E Application Circuits V DD 0 .0 1 m F * 100kW 0 .1 m F 10kW VDD RES PA0~PA2 P A 3 /P F D P A 4 /T M R P A 5 /IN T PA6~PA7 V DD 470pF R OSC OSC1 fS YS R C S y s te m O s c illa to r 30kW /4 OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r P B 0 /A N 0 S C L /P B 3 /A N 3 S D A /P D 0 /P W M ~ C1 OSC C ir c u it S e e R ig h t S id e OSC1 OSC2 C2 R1 OSC2 OSC C ir c u it H T 4 6 R 4 6 E /H T 4 6 C 4 6 E The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator C1, C2 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.30 25 July 19, 2005 HT46R46E/HT46C46E Instruction Set Summary Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rev. 1.30 26 July 19, 2005 HT46R46E/HT46C46E Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (2) (3) (1) (4) Rev. 1.30 27 July 19, 2005 HT46R46E/HT46C46E Instruction Definition ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m] Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] Rev. 1.30 28 July 19, 2005 HT46R46E/HT46C46E AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m] Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m] Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.30 29 July 19, 2005 HT46R46E/HT46C46E CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0 Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) CLR WDT1 Description Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR WDT2 Description Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.30 30 July 19, 2005 HT46R46E/HT46C46E CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Operation Affected flag(s) Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 DECA [m] Description Operation Affected flag(s) Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.30 31 July 19, 2005 HT46R46E/HT46C46E HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1 Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] Rev. 1.30 32 July 19, 2005 HT46R46E/HT46C46E MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] Rev. 1.30 33 July 19, 2005 HT46R46E/HT46C46E RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RETI Description Operation Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RL [m] Description Operation Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RLA [m] Description Operation Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.30 34 July 19, 2005 HT46R46E/HT46C46E RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) RR [m] Description Operation Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRA [m] Description Operation Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRC [m] Description Operation Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rev. 1.30 35 July 19, 2005 HT46R46E/HT46C46E RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SDZA [m] Description Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Rev. 1.30 36 July 19, 2005 HT46R46E/HT46C46E SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1 Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SIZA [m] Description Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SNZ [m].i Description Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.30 37 July 19, 2005 HT46R46E/HT46C46E SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1 Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4 Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.30 38 July 19, 2005 HT46R46E/HT46C46E SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZ [m].i Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) TABRDL [m] Description Operation Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.30 39 July 19, 2005 HT46R46E/HT46C46E XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m] Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x Rev. 1.30 40 July 19, 2005 HT46R46E/HT46C46E Package Information 18-pin DIP (300mil) Outline Dimensions A 18 B 1 10 9 H C D E G F a I Symbol A B C D E F G H I a Dimensions in mil Min. 895 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 915 260 135 145 20 70 3/4 315 375 15 Rev. 1.30 41 July 19, 2005 HT46R46E/HT46C46E 18-pin SOP (300mil) Outline Dimensions 18 A 1 10 B 9 C C' G H D E F a Symbol A B C C D E F G H a Dimensions in mil Min. 394 290 14 447 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 460 104 3/4 3/4 38 12 10 Rev. 1.30 42 July 19, 2005 HT46R46E/HT46C46E Product Tape and Reel Specifications Reel Dimensions T2 D A B C T1 SOP 18W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2 Rev. 1.30 43 July 19, 2005 HT46R46E/HT46C46E Carrier Tape Dimensions D E F P0 P1 t W C B0 D1 P K0 A0 SOP 18W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0+0.3 -0.1 16.00.1 1.750.1 11.50.1 1.50.1 1.5+0.25 4.00.1 2.00.1 10.90.1 12.00.1 2.80.1 0.30.05 21.3 Rev. 1.30 44 July 19, 2005 HT46R46E/HT46C46E Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.30 45 July 19, 2005 |
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